Technical Reference Manual
Internally the Organiser consists of two circuit boards. The system board holds all the digital electronics and has integral interfaces to the display and keyboard. The power supply board controls power regulation and distribution to the system and also carries connectors to the I/O slots and buzzer. The two boards are connected together by a 27 way strip connector.
This section describes the system board hardware, and the following two sections complete the Organiser hardware description.
The System board is a CMOS 8 bit computer including the following:
The board has been engineered to minimise space and power requirements. Small size is achieved through the extensive use of surface-mounted components and by design of a semi-custom IC to perform control functions. Low power is achieved by the use of CMOS circuitry throughout and by taking advantage of the special power saving modes of the processor.
This section describes the circuit in general terms, and specific areas are covered in more detail later.
There are 8 positions for ICs on the board, some of which are optional to provide different memory configurations. All ICs are CMOS with low power standby modes, and all are surface-mounted.
IC1 is the HD6303XFP microprocessor in an 80-pin flat package. This is an 8 bit processor derived from the 6800 family, with standard 8 bit data and 16 bit address busses. In addition it has three 8 bit I/O ports inbuilt. An oscillator provides an input frequency of 3.6864 MHz, which is divided by four internally to an operating frequency of 0.9216 MHz. Processor startup and shutdown are controlled by the STBY_B and RES_B signals from the control IC.
IC2 and IC3 control the LCD display. The HD44780 (IC2) is the master driver with inbuilt character-generator ROM and display data RAM. On the LZ, it was replaced by a customised 66780 chip. The LCD is accessed in the processor memory-map, decoded by the EOUT signal from the control IC. IC3 is a slave driver to extend display width to 16 (20) characters. The LCD plate is mounted to the board through conductive rubber connector strips. The display has either two rows of 16 characters (models CM, XP) or four rows of 20 characters, with each character as an 8 by 5 dot matrix.
IC4 is a semi-custom IC to supervise circuit operation. It's main functions are:
The control IC is reset on "cold start" i.e. when power is first applied to the board.
Power to the board is supplied through the VCC1, VCC2 and V_LCD rails from the power supply. VCC1 is always present and powers all circuit ICs except the LCD drivers. Power consumption is typically 30 microamp when the Organiser is off, mainly due to the real-time clock oscillator. RAM data in both the processor and external RAM devices are retained in this mode. When the Organiser is on (ON_B low) the VCC2 and V_LCD rails are switched on to power the LCD drivers. Contrast adjustment is achieved by adjusting the V_LCD voltage. Power consumption in this state can be 20 milliamp with the processor running code, reducing to 4 milliamp when the processor is set into its "sleep" mode. Capacitors C6-C8 decouple the VCC1 rail.
The HD6303XFP processor is a member of the 6301-6303 family (which are CMOS parts derived from the 6800 series). This member is a ROMless part with a full 64k external memory-map, 1 MHz maximum operating speed and mounted in an 80 pin flat package.
The processor has five operating states: standby, reset, active, halt and sleep. The Organiser does not use halt mode, and reset is only used during the switch-on sequence as a transition between standby and active. The three remaining states are used in the following way:
Processor ports 1,3,4 and 7 control the memory-map. Ports 1 and 4 form the 16 bit address bus A0-A15, port 3 the 8 bit data bus D0-D7, and port 7 supplies the control lines R_B, W_B and R/W_B. External access cycles are decoded and synchronised with the E clock by the control IC.
The memory map is assigned in four address areas:
External devices are described further in the following sections.
System software is carried on the board in the form of ROM (strictly speaking they are One-time programmable CMOS ')"; onMouseout="hideddrivetip()"> EPROM devices). Four options are catered for:
Note that in all options the processor restart and interrupt addresses at the top of the memory-map are included in the ROM area.
The ROMs used are byte-wide CMOS devices in 28 pin flat packages, with access times of 250 ns or better. The types used are:
ROMs installed are powered at all times, and have a typical power consumption in standby mode (with the CS_B pin high) of 1 microamp.
As with the ROM above, there are different options for RAM in the memory map:
Note that address $2000 is used by the system for the start of system variables by all options.
The RAMs used are byte-wide CMOS devices in 28 pin flat packages, with access times of 250 Ns or better. The types used are:
RAMS installed are powered at all times, and hence retain their data when the Organiser is off. In the standby mode their power consumption is typically 2 microamp.
For the more than 16 kbyte options, a bigger chip is used but the bottom 1 kbyte ($0000-$03FF) is never accessed.
In addition to the RAM devices above, their are two other areas of RAM on the board and common to all options:
The six memory selection signals from the control IC (CS1_B to CS6_B) are mapped to the following memory areas:
They are normally high, and go to their active-low state when the relevant memory area is addressed by the processor. These six outputs cover all ROM/RAM options, and a maximum of four can be used at any time.
Note that the links options below are valid for models CM,XP and LA only (they may also be valid for the models LZ and LZ64 but there is no technical information available).
Links L1-L8 on the board are used to match the correct signals to the available memory options. They are arranged as four pairs: L1-L2, L3-L4, L5-L6, and L7-L8. Of each pair only one should be fitted, with the other left open-circuit
If a 32 kbyte ROM is fitted in IC5 then links L1 and L4 should be fitted. L1 routes CS1_B to the ROM to decode it in the $8000-$FFFF range. L4 makes the A14 address line available to the ROM.
If an 8 kbyte ROM is fitted in IC5 then links L2 and L3 should be fitted. L2 routes CS2_B to the ROM to decode it in the $E000-$FFFF range. L3 pulls the ROM pin 27 high since A14 is not required.
If a 32 kbyte RAM is used in IC8 then L6 should be fitted, to route the CS6_B signal to the RAM and decode it in the $0400-$7FFF range.
If an 8 kbyte RAM is used in IC8 then L5 should be fitted to route the CS5_B signal to the RAM and decode it in the $2000-$3FFF range.
Links L7 and L8 set the state of the control IC CTRL input. L7 is normally fitted, and in this case the CS1_B to CS6_B outputs are internally gated with the processor E clock so that they are active only when the E clock is high. If L8 is fitted the decode outputs are dependent on the address lines only.
The bank-switching is carried out by accessing the following addresses (reading or writing):
Note that the operating system may switch ROM banks when any system service is called and during interrupts.
The previous sections have covered memory areas $0000-$0100 (processor internal functions) and $0400-$FFFF (memory devices). The area between these ($0100-$03FF) is used to decode the LCD and latches within the control IC. The control IC decodes these from its address inputs A6-A15, and since A0-A5 are not available each function must span addresses in blocks of 64 bytes or multiples of this. The functions and their address ranges are:
The LCD ENABLE function is a simple decoding one which is output to the EOUT signal on pin 39. This is normally low, and is set high when any address in the range is selected. The LCD is covered further in section LCD display. All the other functions listed perform actions within the control IC which are address-controlled, latched events. Address-controlled means that any processor access to an address within the range will cause the event, irrespective of whether it is a read or write access or of data on the data bus. Once an access has occurred, the affected latch remains in the state set until a further access alters it. If a latch is set, then further accesses to set it will have no effect and a reset access is required to change its state.
The PULSE output is a control signal to the power supply board, used in generating the voltages necessary to program datapacks. It is controlled by an internal PULSE latch. When set, the PULSE signal is enabled and a 32 kHz square-wave signal of between 40-60 percent duty cycle is output to the PULSE output pin. When reset, the output is disabled and is low. The latch is automatically reset when the Organiser is off.
Caution should be used when accessing the PULSE latch, as damage could occur to the power supply if it is left enabled for too long. PULSE is only used by the Organiser during datapack programming, and in a strictly controlled loop using the READY signal as a feedback input. In this loop, PULSE is disabled as soon as the READY input goes high. This is discussed further in the power supply section.
The ALARM signal is a direct output from the ALARM latch. It is used to drive the piezoelectric buzzer element mounted from the power supply board.
When the ALARM latch is set, the output signal goes high and the voltage is applied across the buzzer element. When reset, the signal is removed. ALARM may be left in either state, but the buzzer only produces sound at transitions between the two states. To produce a tone, the software must access the ALARM set and reset functions alternately to produce the frequency required.
The alarm signal is also used as an interlock in the power supply circuit, to allow datapack programming voltages to be applied to the packs. This is described further in the power supply section.
The real-time clock and keyboard poll are both functions dealt with by the control IC. Although at first sight they are completely independent functions, they are linked together in the control IC since the keyboard poll outputs K1-K7 are part of the clock divider chain. For this reason they are described together in this section.
The clock divider chain is implemented in the control IC as a 27 bit binary counter split into two stages:
Stage 1 is a 15 bit free-running binary counter clocked by the 32768 Hz oscillator input. Each cycle of the clock increments the counter, and when all bits are high the next cycle resets them all to low. In other terms, each bit of the counter alternates high and low at a frequency of one half the previous bit. Hence the last bit, bit 15, oscillates at a frequency of 1 Hz.
Three of the bits of this stage may appear at output pins:
Stage 2 is a 12 bit binary counter which may be clocked from one of two sources: either from the 1 Hz signal if NMI is disabled, or by a processor access to the COUNTER CLOCK area of its memory-map. In addition this stage may be reset by an access to the COUNTER RESET function. Eight of the twelve bits of this stage appear at the output pins. Bits 1-7 appear as the keyboard poll outputs K1-K7 respectively. Since they are open-drain outputs they are pulled low when the counter bits are low, and float when the counter bits are high. Bit 12 appears as the ACOUT signal, and when high internally sets the ON/OFF latch to start a switch-on sequence.
With the two stages linked together (i.e. with NMI disabled), the last bit (ACOUT) would have a cycle time of 68 mins 16 secs if left as a free-running counter. In practice the counter is never left to free run, and if started from a reset condition is interrupted after half a cycle (34 mins 8 sec) when it switches the Organiser on.
The date and time are kept and updated by the processor in its internal RAM. When the Organiser is on, it is normally receiving an NMI interrupt every second, and so can update the time on a second by second basis. Clearly when the Organiser is off this cannot be done, and in this case the stage 2 counter is used instead to keep track of elapsed time since the Organiser was switched off.
To explain this process, imagine that the clock is set exactly with the processor running and receiving NMI interrupts every second. The time is incremented immediately following each interrupt. When the Organiser switches off it follows the following sequence:
The next and subsequent 1 Hz cycles will increment the stage 2 counter, and this will continue for 34 mins 8 secs until the last bit (ACOUT) is set high. This starts the switch-on sequence to restart the processor. When running, the processor enables the NMI latch to start updating the clock directly every second. It also reads the state of the ACOUT signal, and because it is high it knows the clock is 34 minutes 8 seconds slow, and adds this to its time registers. Hence the time and date are accurate again and being updated every second.
This explains the general mechanism of keeping time when the processor is off, using the stage 2 counter. A few other details need clarifying to explain the system fully:
The AC key at the keyboard top left is a special case since it is used to switch the Organiser on. As such it is the only key on the keyboard whose function cannot be totally software defined. The AC key switches the AC signal on the board, and is input both to the control IC AC input and to the processor port 5 bit 7. It is normally low, and is pulled high on pressing the key. Pressing AC when the Organiser is off will set the ON/OFF latch in the control IC and start a switch-on sequence. When the processor is running, it polls this key by reading port 5 bit 7 (1=AC pressed, 0=AC not pressed). The external AC input from the Organiser top slot is in parallel with the AC key. This is used to switch the Organiser on from an external input, but it is disabled whenever the ON/OFF latch is set and so cannot be polled.
The other 35 keys on the keyboard are arranged as a 7 by 5 switch matrix. They are polled using the K1-K7 outputs from the control IC and the KBD1-KBD5 inputs to the processor port 5. The inputs are normally high, and are pulled low when a key is pressed and the relevant output is set low. The keys are arranged in the following way:
To poll the matrix, the processor first resets the stage 2 counter. All outputs K1-K7 will now be pulled low and all rows of the matrix accessed simultaneously; i.e. if any key is pressed then one of the port 5 inputs will be pulled low. Conversely, if all inputs are high then no keys are pressed and no further polling is required. If a key press is detected at this stage then the processor polls each row of keys in turn to isolate which key is responsible.
To do this it accesses the COUNTER CLOCK address until the K7 output is low but K1-K6 are all floating. The first row of the matrix above are now accessed, and depression of the D,J,P,V or S keys is detected if a low is present at the corresponding bit of port 5. To poll the next row, more COUNTER CLOCK accesses are required until the K6 output is low with K7 and K1-K5 floating. This process is repeated 7 times until all rows have been read.
Because this process uses the stage 2 counter, the keyboard can only be polled when the NMI latch is set to directly interrupt the processor.
The following paragraphs describes the operation of the two-line models:
The display on the LZ and LZ64 uses the same LCD drivers as on the standard Organiser but is arranged as 4 lines by 20 characters and the HD44780 was replaced by a customised HD66780 chip to allow for a customized character set.
The display is accessed by the processor in the memory area $0180-$01BF as described above. The two registers are selected by the A0 address line, so even addresses in this range access the Instruction Register, odd ones the Data Register. The 8 bit mode is used to transfer data to the processor, and this must be selected when the drivers are initialised.
The display drivers and LCD plate are powered by the VCC2 and V_LCD rails from the power supply board. These are switched off whenever the Organiser is off, and so the LCD must be initialised at each processor startup. The intermediate voltages required are provided by the resistor chain R1-R5. Contrast adjustment is controlled by the thumbwheel on the power supply board, by adjusting the V_LCD voltage between limits of +0.6 and -3 volts. Power required is typically 2 milliamp from VCC2 and 0.5 milliamp from V_LCD.