How to Build a Parallel Interface

How to build a Parallel Interface

Dr. Andrew Smith

 

This document describes how the three slots of the Psion II can be controlled by assembly language routines, and how a parallel I/O facility providing up to eight 8-bit parallel I/O devices can be connected to a slot. Example assembly-language device-driver routines are included. The system can be used with OPL routines running on the Psion if this approach is required.

General Slot Control

Parallel interfacing to the Psion II can be effected via any of the three interface slots - the Topslot, or the memory pack slots B or C. These slots carry signals derived from two on-chip parallel I/O ports on the 6303 CPU. Interfacing is achieved by manipulating these ports with machine code routines running in the Psion's RAM. It is not realistic to attempt to manipulate the ports directly using OPL programs, although short machine code routines can be written which are then called using the OPL USR function. This technique can make the ports accessible to OPL programmers: examples of suitable assembler routines are given later.

The 6303 ports of interest are port 6 and port 2. Both are 8-bit parallel I/O ports, and each has a data register and an associated data direction register (ddr). Writing $FF to a ddr makes the related data port an output, while writing 0 to a ddr makes the port an input. Addresses are given below:

 

Register Address
Port 2 DDR 1
Port 2 Data (P2D) 3
Port 6 DDR $16
Port 6 Data (P6D) $17

 

P2D is available directly on the Psion's slots and is the port through which external data exchanges are made.

Since the port is common to all three slots it forms a kind of peripheral data bus, and data on it is therefore presented to all devices in any slot. This means that the data is transitory, and is must be addressed to a specific device in a specific slot at a specific time. Slot devices must latch output data, or enable input data under the control of ancillary control signals. P6D controls these signals.

Names of signals and allocation to ports

Slot data signals (the peripheral data bus) are designated SD0 to SD7 and correspond to Port 2 signals P2-0 to P2-7 respectively.

Slot ancillary control signals have the following names - SS1, SS2, SS3, SOE, SMR, SCK, SVCC, SPGM, and are derived from P6D as follows:

 

Port 5 Bit 7 6 5 4 3 2 1 0
Signal SVCC SS3 SS2 SS1 SOE SPGM SMR SCK

 

The functions of these signals will be described later, but at this stage it is worth noting that the most critical signals from the point of view of the programmer are SS1 to SS3. These are used as low-active Slot Select signals. Only one of these is available at each slot, a different one in each case. SS3 is present on the Topslot, SS1 on Slot B and SS2 on Slot C.

It is most important that the programmer only writes one of these low at any time, since the signals are used to enable slot devices, and if two or more devices are simultaneously enabled data contentions will occur. These signals are held high even when the Psion is switched off.

Slot Pinouts

Top Slot



Fig 1. Top Slot (Slot 3)

 

Pin 15 13 11 9 7 5 3 1
Signal SOE SVCC SVB GND SD4 SD5 SD6 SD7
SMR AC SS3 SCK SD3 SD2 SD1 SD0
Pin 16 14 12 10 8 6 4 2

 

Side Slots



Fig 2. Slots B (1) and C (2)

 

Pin 16 14 12 10 8 6 4 2
Signal SVPP SPGM SS1/2 SCK SD6 SD4 SD2 SD0
SVCC GND SOE SMR SD7 SD5 SD3 SD1
Pin 15 13 11 9 7 5 3 1

 

Signal Descriptions

Name Description
AC Topslot External On/Clear.
Ground this to turn the Psion on.
GND 0v
SD0
-
SD7
Parallel I/O Peripheral Bus (P2D)
SCK Peripheral Control lines - see below
SMR
SOE
SPGM Program enable for